The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effectively applicable to an LSI (Large Scale Integration) having a logic circuit block and a memory block formed on a single semiconductor substrate.
As a prior art semiconductor integrated circuit device having a logic circuit block and a memory block, it is known to providing at an end portion of a main surface of a rectangular semiconductor chip a RAM (Random Access Memory) and with a logic circuit block at a center of the chip as described in "BiCMDS Technology," Seiji Kubo, Sep. 20, 1990, pp 146 to 151, Electronic Information Communications Association, for example.
The present invention also relates to a method of laying out many functional circuit blocks on a chip of a semiconductor integrated circuit device and, more particularly, to a technology effectively applicable to a semiconductor integrated circuit device such as a gate array composed of an ECL (Emitter Coupled Logic) circuit and the like.
For designing technique of an ASIC (Application Specific Integrated Circuit), a standard cell method is known. In the standard cell method, standard cells previously designed are assembled to design an entire chip. Such a standard cell method is described in Nikkei Electronics, Sep. 9, 1985, pp 165-169 and 175-176, Nikkei-McGraw-Hill.